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OCZ / Enhanced Bandwidth Technology
Enhanced Bandwidth Technology
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Summary: Enhanced Bandwidth (EB) technology is a means of increasing memory bandwidth through the optimization of memory latencies for the best possible interaction between the system memory and the chipset and memory controller. Through thorough analysis of memory traffic and benchmark results under various operating conditions as defined by different memory latency settings in the CMOS setup of the BIOS, we have pinpointed the bottlenecks relevant for performance. Some conventional wisdom regarding some memory latencies were also found to no longer hold true. Using those findings, we redesigned our memory products to be optimized for delivering the highest possible bandwidth to any computer system.
Memory bandwidth is influenced by two major factors?frequencies and latencies.
Transfer frequency, or data rate, is important since the theoretical peak bandwidth is defined by the bus width (in number of bits) multiplied by the frequency. Theoretical peak bandwidth is defined as the physical limit of the number of bytes that can be transferred from sender to receiver without counting idle bus periods. Thus, with a fixed bus width, the total theoretical peak bandwidth is a factor of the operating frequency alone.
In real life, however, this equation is not adequate. No computer system, regardless of how well it is optimized, is able to achieve peak transfer rates in a sustained fashion since only a limited number of back-to-back transactions can be carried out. Initial access latencies, along with memory-internal parameters such as page boundaries within the memory devices, pose an effective barrier to the actual peak bandwidth.
Some memory benchmarks work around these problems through implementation of prefetch algorithms to utilize the in-order queues?i.e. pipelined prefetch buffers on the chipset, along with bank interleaving on the memory device itself. The result is approximately 90 to 95% bus utilization based on the idea that recurrent access latencies can be hidden behind already pipelined data output from either I/O buffers on the DIMMs or the chipset. This is why some benchmarking programs return ?inflated? bandwidth scores that do not accurately reflect real world applications.
However, in most real world applications, only a small fraction of accesses stay ?in page?? meaning that the requested data are found within the address range of the currently open memory page. The ratio of page hits vs. page misses varies from one application to another. In network router and server applications, accesses are mostly random and result in almost no page hits, whereas a memory address pattern analysis we conducted demonstrated that in streaming video editing or gaming applications the number of page hits can reach 70 to 80%.
In most cases, the memory access pattern follows the general scheme that one page is opened with a row access and, subsequently, a small number of column addresses within that page get hit. Each page hit specifies a block of 64 column addresses that results in an output of eight transfers of eight bits each (in the case of an x8 memory device). In interleaved mode, subsequent blocks do not need to follow a contiguous column address pattern as long as the sequence is predetermined. This is important for the understanding how, within a given page, the Column Address Strobe (CAS) can jump back and forth between higher and lower addresses without missing the page. However, given the limited number of column addresses within each page, there is a limit to how many page hits can occur before a page boundary is finally met and the next memory request will miss the currently open page.
Figure 1: Schematic overview of an internal bank of a memory device: After a row has been selected and activated (highlighted area on left), the Column Address Strobe can select a block of logically coherent addresses within this row (right). The number of page hits is limited among other factors by the limited number of column addresses within each page. Note that per DRAM convention rows are running vertically and columns horizontally.
Picture courtesy of LostCircuits
Every such page miss will result in a complicated sequence of events. First, the currently open page must be closed. Since a read from a DRAM memory cell is destructive, data that were read out to the primary sense amplifiers within the array must be written back to the memory cells, after which the RAS lines need to be precharged. Closing a page takes between two and four clock cycles, during which time no other page can be activated. Only after a ?virgin? state of the memory array has been re-established can the next Row Activate command be issued. The performance penalties stemming from a precharge in an open-page situation will vary in severity depending on the number of latency cycles associated with the precharge-to-activate delay (tRP), because the number of number of latency cycles of tRP will determine the number of ?No Operation? (NoOp) cycles during which no data can be transferred. Keep in mind that with a Double Data Rate (DDR) protocol, the penalties are doubled since each idle cycle causes a delay or miss of two transfers resulting in a severe reduction in effective bandwidth.
Before the next page hit can occur, another page needs to be opened which includes a sequence that is the reverse of the precharge. First, a row address is decoded, followed by the row access strobe moving to the respective row address to pull the signal low for a logical true. This, in turn, opens the pass-gates to all memory cells within this row. The memory cells then discharge their contents to the primary sense amplifiers. After a voltage differential for each bitline pair has been sensed and amplified, a read command is issued. The time taken for this entire process is the RAS-to-CAS delay (tRCD). Both tRP and tRCD are the two main factors that cause a reduction in effective memory bandwidth.
Figure 2: Timing diagram for two modules, one running at TRCD-4, CL-2.5, tRP-4 (bottom) and the second with tRCD-3, CL-2.5-tRP-2 (top) showing two consecutive bursts of 8 from two different pages which is one of the most common scenarios in real world applications The effective bandwidth is the ratio between data transfers (black diamonds): NoOps (red arrows) which, in the case of EB is 8:7 without EB, this ratio is 8:10, meaning that every transfer of 16 bits is penalized with either 7 or 10 subsequent bus idle cycles.
(Clk: clock; Act: row activate command; Rd: read command; Pr: Precharge command, NoOp: No Operation)
On average, there are three to four page hits following an initial page access. In those cases, the CAS latency (CL) determines the number of penalty cycles incurred between the read command and the start of data output to the bus. However, a read command can be issued concurrent with an ongoing data burst. This means that the read command for the next data burst can be issued before an ongoing data transfer is exhausted with the result that the latency cycles are hidden behind the previous transfer. CAS latency (CL), therefore plays a much smaller role in limiting bandwidth than RAS-to-CAS Delay or Precharge latency.
The diminished importance of CL is in contrast, though, to conventional wisdom that has labeled CL as the most important memory latency. However, this used to hold true for single data rate SDRAM, which is the reason why, until recent years, most memory manufacturers only listed their CL specifications and not the other latency parameters.
Figure 3: The effect of issuing an early Read Command on back-to-back transactions of consecutively requested data blocks within the same page. Following one Row Activate Command, three Read commands are given at a CAS Latency of either 2, 2.5 or 3. The colored diamonds are the data transfers that belong to the Read Command in the same color. The graph shows that the net effect of increasing the CAS latency is a single cycle delay within a string of (in this case) 12 consecutive transfers but no degradation of bandwidth. The double-arrows indicate the CAS latency which is amended by moving the read command further to the left (relative to the end of the previous burst). (Clk: clock; Act: row activate command; Rd: read command; Pr: Precharge command, CL: CAS Latency)
Enhanced Bandwidth technology further capitalizes on another feature possible in DDR through the Variable Early Read Command. Early Read Command compensates for higher CAS latencies by changing the time at which a read command is issued relative to an ongoing transfer. More precisely, if there is an ongoing burst of data with a CL=2, the read command is issued two cycles before the end of the burst with the result that the next data output seamlessly follows the previous. With a CL=3, the read command is issued three cycles before the end of the ongoing transfer and this scheme can be extended to higher CAS latencies as well. Therefore, within any page, the bandwidth reduction by an increased CL is negligible.
The Enhanced Bandwidth series uses low tRP and tRCD latencies in combination with a Variable Early Read Command to allow for the highest possible effective data bandwidth. In most applications, the 2.5-2-3 (CL-tRP-tRCD) will deliver bandwidth that is indistinguishable from CL-2 modules.
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